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NXP Semiconductors /LPC43xx /CGU /IDIVA_CTRL

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Interpret as IDIVA_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLED)PD 0 (RESERVED)RESERVED 0 (DIV1)IDIV 0 (RESERVED)RESERVED0 (DISABLED)AUTOBLOCK 0 (RESERVED)RESERVED0 (32_KHZ_OSCILLATOR)CLK_SEL0 (RESERVED)RESERVED

PD=ENABLED, CLK_SEL=32_KHZ_OSCILLATOR, AUTOBLOCK=DISABLED, IDIV=DIV1

Description

Integer divider A control register

Fields

PD

Integer divider A power down

0 (ENABLED): Enabled. IDIVA enabled (default)

1 (POWER_DOWN): Power-down
RESERVED

Reserved
IDIV

Integer divider A divider values (1/(IDIV + 1))

0 (DIV1): 1 (default)

1 (DIV2): 2

2 (DIV3): 3

3 (DIV4): 4
RESERVED

Reserved
AUTOBLOCK

Block clock automatically during frequency change

0 (DISABLED): Disabled. Autoblocking disabled

1 (ENABLED): Enabled. Autoblocking enabled
RESERVED

Reserved
CLK_SEL

Clock source selection. All other values are reserved.

0 (32_KHZ_OSCILLATOR): 32 kHz oscillator

1 (IRC): IRC (default)

2 (ENET_RX_CLK): ENET_RX_CLK

3 (ENET_TX_CLK): ENET_TX_CLK

4 (GP_CLKIN): GP_CLKIN

6 (CRYSTAL_OSCILLATOR): Crystal oscillator

7 (PLL0USB): PLL0USB

8 (PLL0AUDIO): PLL0AUDIO

9 (PLL1): PLL1
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data